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Centre Notifies ₹1.27 Lakh Crore Semicon 2.0 Scheme to Boost Semiconductor Ecosystem
The government formally notified the Semicon 2.0 scheme with an outlay of ₹1.27 lakh crore, aiming to deepen India's semiconductor ecosystem. The scheme provides fiscal support across chip design, fabs, packaging, and more, with IT Secretary S. Krishnan stating its objective of self-reliance and fostering a globally competitive industry.
By Tertius News AI Desk6 distinct · 9 mastheads · 9 articlesVersion 2Coverage Published
The government has formally notified the Semicon 2.0 scheme, an outlay of ₹1.27 lakh crore aimed at deepening India's semiconductor ecosystem. The scheme, approved by the Union Cabinet and notified on August 31, 2026, provides sustained policy support for the development of semiconductor design and manufacturing capabilities in the country.
The scheme has been divided into six segments covering designing of chips by Indian firms, setting up units for capital equipment required for chip production, semiconductor fabs, chip assembly, packaging and testing, among others. It is designed to support the entire value chain of the semiconductor industry.
IT Secretary S. Krishnan said at a briefing: "The objective of the scheme is self reliance and fostering a globally competitive industry." He added, "Now the time is ripe to move to next stage to develop semiconductor ecosystem through Semicon 2.0."
The scheme provides fiscal support across several categories. For silicon semiconductor wafer fabs, the government will provide 40% of eligible capital expenditure on a pari-passu basis. For compound semiconductors, silicon photonics, and sensors (including MEMS) fabs, fiscal support will be 30%. Advanced packaging technologies, including 2.5D and 3D packaging, wafer-level chip-scale packaging, and heterogeneous integration, will receive 35% support. Legacy packaging projects will get 25% support.
The scheme also covers semiconductor design, with support for Indian companies owned/controlled by Indian citizens or entities. The government will provide up to 50% of eligible capital expenditure for setting up or modernising semiconductor fabs, with a cap of ₹1,200 crore per fab. For compound semiconductor, silicon photonics, and sensor fabs, the support is 30% of eligible capital expenditure, capped at ₹600 crore per project.
According to the scheme's guidelines, the government will provide 40% fiscal support for silicon semiconductor wafer fabs. For advanced packaging technologies such as 2.5D and 3D packaging, wafer-level chip-scale packaging, and heterogeneous integration, the government will provide 35% of eligible capital expenditure. Legacy packaging projects will receive lower support of 25%.
Under Semicon 2.0, Indian companies owned or controlled by Indian citizens or companies, including startups and MSMEs, are eligible. Startups can receive financial support in the form of grant, equity, or debt. The scheme also covers companies designing chips for automotive, AI, and other sectors, with support for up to 50% of the eligible capital expenditure.
The scheme is expected to run for six years, with an initial application window of three years. The India Semiconductor Mission (ISM) will act as the nodal agency for implementing this scheme. According to the Cabinet presentation, the government projects ₹2 lakh crore in production and ₹1 lakh crore in exports from the semiconductor program over the next six years.
The government's notification states: "Semicon 2.0 provides fiscal support to various segments of the semiconductor industry, ranging from chip design, fabrication and packaging to various segments of the semiconductor ecosystem." The scheme aims to build resilient, trusted, and sovereign semiconductor technologies by focusing on designing, development, and deployment of target segment technologies for national strategic and critical infrastructure.
The move comes amid growing global concerns over supply-chain vulnerabilities and unprecedented demand for semiconductors, positioning India to capitalise on the shifting dynamics of the global semiconductor industry.
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Framing: Highlights the government's notification of a large-scale scheme to boost the chip sector.
Facts Included:
The scheme has been divided into six segments covering designing of chips by Indian firms, setting up units for capital equipment required for chip production, semiconductor fabs, chip assembly, packaging and testing, etc.
The scheme will aim to build resilient, trusted, and sovereign semiconductor technologies by focusing on designing, development, and deployment of target segment technologies for the national strategic and critical infrastructure.
It will target local development of semiconductor Intellectual Property (IP) cores, Chips, System-on-Chips (SoCs), and modules for electronic products, as may be identified from time to time based on national importance and strategic priorities.
To achieve this, building blocks will be developed, including standard IPs for various types of Compute, Memory, RF, Power, Networking, Sensors.
Chip-design startups can receive up to ₹15 crore seed funding and use national EDA tools and multi-project wafer fabrication.
Advanced R&D and talent-development projects receive up to 75% of project cost.
The government approved 12 semiconductor projects under the first phase, with Micron's ATMP plant, Kaynes Semicon, and CG Semi's OSAT facility already in commercial production.
Framing: Announces the formal notification of Semicon 2.0 and its large financial outlay. — Neutral and factual, with a positive emphasis on the scheme's objectives and progress.
Facts Included:
The Centre on Monday formally notified Semicon 2.0 with a Rs 1.27 lakh crore outlay.
The plan seeks to deepen India’s semiconductor ambitions.
The scheme opens the next phase to a wider set of companies and institutions, including chip-design start-ups, MSMEs, semiconductor fabs, packaging companies, materials manufacturers, research organisations, and training institutions.
The Ministry of Electronics and Information Technology (MeitY) has divided eligible applicants into six pillars and 10 categories.
IT secretary S Krishnan stated the objective is self-reliance and fostering a globally competitive industry.
Financial support for design includes grants and equity co-investment for start-ups, and royalty financing for companies.
For fabs, fiscal support is 40% for silicon fabs and 35% for compound, display, and other specialised fabs.
For packaging, incentives are 35% of capex for advanced packaging and 25% for conventional packaging.
Under the first phase, the government approved 12 semiconductor projects across six states; three facilities (Micron's ATMP plant, Kaynes Semicon, CG Semi OSAT) commenced production earlier this year.
Framing: The headline emphasizes the notification of Semicon 0 as a policy move to widen India's semiconductor initiative beyond manufacturing. — The tone is factual and promotional, presenting government announcements and projections without critical analysis.
Facts Included:
Electronics and IT Minister Ashwini Vaishnaw said India had achieved its earlier target of developing 85,000 semiconductor engineers in four years, against 10 years originally envisaged.
Vaishnaw said India now aims to add another one lakh engineers as the global semiconductor industry faces a growing shortage of skilled workers.
Vaishnaw projected close to 10% of the global semiconductor market could be in India, and noted that students from Tier-II and Tier-III cities have designed over 250 chips.
The government has expanded its semiconductor design programme to 355 universities, including institutions in Tier-II and Tier-III cities.
The programme is structured around six pillars: design, equipment and materials, fabrication, ATMP/OSAT, R&D, and talent development.
For large silicon wafer fabrication plants, the Centre will provide fiscal support of 40% of eligible capital expenditure, compared with 50% under the earlier programme.
Projects will require a minimum investment of ₹20,000 crore.
Vaishnaw said the reduction in support reflected greater state government support and progress made under the first phase.
Smaller fabs in areas such as compound semiconductors, silicon photonics, and sensors, with a minimum investment of ₹500 crore, will be eligible for 35% support.
Display fabs manufacturing OLED, Micro LED, or LCD panels will be eligible for incentives of up to 35%, subject to prescribed capacity thresholds.
Advanced packaging facilities using technologies such as 5D/3D packaging, wafer-level chip-scale packaging, and heterogeneous integration will receive support of up to 35% of eligible capital expenditure; conventional ATMP/OSAT plants will get 25%.
Support for semiconductor equipment and materials is a significant addition, with 30% capital expenditure support for R&D facilities, manufacturing of semiconductor-grade raw materials, testing, characterisation, equipment manufacturing, and assembly.
Equipment and component manufacturers can receive production-linked incentives of 2-10% based on domestically sourced component value for five years beginning FY29.
For strategic-sector chips, development will be through a competitive request-for-proposal process run by C-DAC, with IP jointly owned by C-DAC and the applicant; C-DAC cannot commercially exploit the shared IP unless the company fails contractual obligations.
Startups and MSMEs in commercially oriented chip design can receive milestone-linked seed funding of up to ₹15 crore or 50% of project cost, access to EDA tools, and multi-project wafer fabrication services; larger companies can opt for royalty-based financing or equity co-investment.
A deployment-linked incentive will reimburse 9% of net sales from newly launched chips for five years, subject to caps.
R&D and talent-development projects can receive support of up to 75% of project costs.
MeitY Secretary S Krishnan said India's semiconductor market, currently about $52 billion, could reach $110-120 billion by 2030; the global market could expand to $1.6 trillion by then and approach $2 trillion by 2035.
India has approved 12 semiconductor manufacturing projects across six states; nine are ATMP/OSAT projects; three have begun commercial production this year, and two more are expected by end of 2026.
Framing: The headline emphasizes the government's notification of the ₹1.27 lakh crore Semicon 2.0 scheme to boost the chip ecosystem.
Facts Included:
The government has notified the Semicon 2.0 scheme with an outlay of ₹1.27 lakh crore.
The scheme has been divided into six segments covering designing of chips, setting up units for capital equipment, semiconductor fabs, chip assembly, packaging and testing.
The scheme will aim to build resilient, trusted, and sovereign semiconductor technologies.
It will target local development of semiconductor IP cores, Chips, System-on-Chips, and modules for electronic products.
Framing: The headline emphasizes the government's notification of the Semicon 2.0 scheme and its ₹1.27 lakh crore outlay to boost the chip ecosystem.
Facts Included:
The government has notified the Semicon 2.0 scheme with an outlay of ₹1.27 lakh crore.
The scheme has been divided into six segments covering designing of chips by Indian firms, setting up units for capital equipment required for chip production, semiconductor fabs, chip assembly, packaging and testing, etc.
The scheme will aim to build resilient, trusted, and sovereign semiconductor technologies by focusing on designing, development, and deployment of target segment technologies for the national strategic and critical infrastructure.
It will target local development of semiconductor Intellectual Property (IP) cores, Chips, System-on-Chips (SoCs), and modules for electronic products.
Framing: The headline emphasizes the government's notification of the Semicon 0 scheme, highlighting its scale (₹1,27,500-crore) and its focus on eligibility norms and incentives for the chip ecosystem. — The tone is neutral and factual, presenting policy details without evaluative language.
Facts Included:
The scheme is a ₹1,27,500-crore plan aimed at deepening India’s semiconductor ambitions.
The scheme covers chip manufacturing and a full-stack ecosystem including indigenous design, IP, equipment, materials, advanced packaging, R&D, and talent development.
The scheme was approved by the Union Cabinet on July 15, 2026.
IT Secretary S. Krishnan said at a briefing that the time is ripe to develop the semiconductor ecosystem.
The scheme offers financial support: for chip design, startups and companies owned by Indian citizens or OCI are eligible, with grants and equity co-investment for startups and royalty financing for companies.
For new fabs, the scheme provides 40% fiscal support for silicon fabs and 35% for compound, display, and other specialised fabs.
For ATMP/OSAT, the scheme supports advanced and legacy packaging with incentives of 35% of capex for advanced packaging and 25% for conventional packaging.
Under the first phase of the programme, the government had approved 12 semiconductor projects across six states, with three facilities (Micron’s ATMP plant, Kaynes Semicon, CG Semi OSAT) having commenced commercial production earlier this year.
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Claim
Confidence
Status
ClaimThe government has notified the Semicon 2.0 scheme with an outlay of ₹1.27 lakh crore (or ₹1.27 trillion).
ClaimThe scheme has been divided into six segments covering designing of chips by Indian firms, setting up units for capital equipment required for chip production, semiconductor fabs, chip assembly, packaging and testing.
ClaimSemicon 2.0 provides fiscal support to various verticals across the complete value chain of the semiconductor industry, ranging from chip design, fabrication and packaging to various segments of the semiconductor ecosystem.
ClaimThe scheme aims to build resilient, trusted, and sovereign semiconductor technologies by focusing on designing, development, and deployment of target segment technologies for the national strategic and critical infrastructure.
ClaimThe scheme targets local development of semiconductor Intellectual Property (IP) cores, Chips, System-on-Chips (SoCs), and modules for electronic products.
ClaimThe notification stated that building blocks will be developed, including standard IPs for various types of Compute, Memory, RF, Power, Networking, Sensors.
ClaimThe government has decided to provide sustained policy support to the semiconductor sector in India by notifying the Semicon 2.0 Scheme for the development of semiconductor design and manufacturing ecosystem in India.
ClaimThe scheme covers a wider range of participants including chip-design startups and MSMEs, semiconductor fabs, packaging companies, materials and equipment manufacturers, research organisations and training institutions.
ClaimIT Secretary S Krishnan said at a briefing: "Now the time is ripe to move to next stage to develop semiconductor ecosystem through Semicon 2.0. The objective of the scheme is self reliance and fostering a globally competitive industry."
ClaimFor startups, financial support will be in the form of grant and equity co-investment, and for companies it would be in the form of royalty financing or equity co-investment.
ClaimFor strengthening ATMP/OSAT, the scheme supports advanced and legacy packaging with an incentive of 35% of capex for advanced packaging and 25% of capex for conventional packaging.
ClaimUnder the first phase of the programme, the government had approved 12 semiconductor projects across six states, with three facilities — Micron's ATMP plant, Kaynes Semicon and CG Semi OSAT facility — having commenced commercial production earlier this year.
ClaimFor silicon wafer fabs, the government will provide 40% of eligible capital expenditure, and applicants must propose a 300-mm wafer facility with capacity of at least 40,000 wafer starts per month, invest at least ₹20,000 crore and have minimum revenue of ₹7,500 crore in at least one of the preceding three financial years.
ClaimFor compound semiconductor, photonics, sensor/MEMS and discrete semiconductor fabs, the minimum investment is ₹500 crore, with minimum revenue of ₹200 crore and capacity of at least 500 wafer starts per month, and these projects will receive 35% of eligible capex.
ClaimFor advanced packaging technologies such as 2.5D and 3D packaging, wafer-level chip-scale packaging, and heterogeneous integration, the government will give 35% of eligible capital expenditure on a pari-passu basis.
ClaimThe government's Cabinet presentation projected around ₹4 lakh crore in investment from the program, ₹2 lakh crore in production and ₹1 lakh crore in exports.
6 distinct · 9 mastheads · 9 articles consulted: Business Standard, Business Today, Deccan Chronicle, The Financial Express, The New Indian Express, NewsBytes, Outlook Business, The Hindu Business Line, The Hindu — World28 claims extractedVersion 2Written 2026-08-31